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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 | # DP: Backport PR target/67281 from the trunk (HTM fixes)
Backport from mainline
2015-10-14 Peter Bergner <bergner@vnet.ibm.com>
Torvald Riegel <triegel@redhat.com>
PR target/67281
* config/rs6000/htm.md (UNSPEC_HTM_FENCE): New.
(tabort, tabort<wd>c, tabort<wd>ci, tbegin, tcheck, tend,
trechkpt, treclaim, tsr, ttest): Rename define_insns from this...
(*tabort, *tabort<wd>c, *tabort<wd>ci, *tbegin, *tcheck, *tend,
*trechkpt, *treclaim, *tsr, *ttest): ...to this. Add memory barrier.
(tabort, tabort<wd>c, tabort<wd>ci, tbegin, tcheck, tend,
trechkpt, treclaim, tsr, ttest): New define_expands.
* config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Define
__TM_FENCE__ for htm.
* doc/extend.texi: Update documentation for htm builtins.
Backport from mainline:
2015-08-03 Peter Bergner <bergner@vnet.ibm.com>
* config/rs6000/htm.md (tabort.): Restrict the source operand to
using a base register.
--- a/src/gcc/doc/extend.texi
+++ b/src/gcc/doc/extend.texi
@@ -14573,6 +14573,28 @@
unsigned int __builtin_tsuspend (void)
@end smallexample
+Note that the semantics of the above HTM builtins are required to mimic
+the locking semantics used for critical sections. Builtins that are used
+to create a new transaction or restart a suspended transaction must have
+lock acquisition like semantics while those builtins that end or suspend a
+transaction must have lock release like semantics. Specifically, this must
+mimic lock semantics as specified by C++11, for example: Lock acquisition is
+as-if an execution of __atomic_exchange_n(&globallock,1,__ATOMIC_ACQUIRE)
+that returns 0, and lock release is as-if an execution of
+__atomic_store(&globallock,0,__ATOMIC_RELEASE), with globallock being an
+implicit implementation-defined lock used for all transactions. The HTM
+instructions associated with with the builtins inherently provide the
+correct acquisition and release hardware barriers required. However,
+the compiler must also be prohibited from moving loads and stores across
+the builtins in a way that would violate their semantics. This has been
+accomplished by adding memory barriers to the associated HTM instructions
+(which is a conservative approach to provide acquire and release semantics).
+Earlier versions of the compiler did not treat the HTM instructions as
+memory barriers. A @code{__TM_FENCE__} macro has been added, which can
+be used to determine whether the current compiler treats HTM instructions
+as memory barriers or not. This allows the user to explicitly add memory
+barriers to their code when using an older version of the compiler.
+
The following set of built-in functions are available to gain access
to the HTM specific special purpose registers.
|