/usr/share/gputils/header/p18f25j10.inc is in gputils-common 0.13.7-1.
This file is owned by root:root, with mode 0o644.
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;==========================================================================
; MPASM PIC18F25J10 processor include
;
; (c) Copyright 1999-2008 Microchip Technology, All rights reserved
;==========================================================================
NOLIST
;==========================================================================
; This header file defines configurations, registers, and other useful
; bits of information for the PIC18F25J10 microcontroller. These names
; are taken to match the data sheets as closely as possible.
;
; Note that the processor must be selected before this file is included.
; The processor may be selected the following ways:
;
; 1. Command line switch:
; C:\MPASM MYFILE.ASM /PIC18F25J10
; 2. LIST directive in the source file
; LIST P=PIC18F25J10
; 3. Processor Type entry in the MPASM full-screen interface
; 4. Setting the processor in the MPLAB Project Dialog
;==========================================================================
;==========================================================================
;
; Verify Processor
;
;==========================================================================
IFNDEF __18F25J10
MESSG "Processor-header file mismatch. Verify selected processor."
ENDIF
;==========================================================================
; 18xxxx Family EQUates
;==========================================================================
FSR0 EQU 0
FSR1 EQU 1
FSR2 EQU 2
FAST EQU 1
W EQU 0
A EQU 0
ACCESS EQU 0
BANKED EQU 1
;==========================================================================
;==========================================================================
; 16Cxxx/17Cxxx Substitutions
;==========================================================================
#define DDRA TRISA ; PIC17Cxxx SFR substitution
#define DDRB TRISB ; PIC17Cxxx SFR substitution
#define DDRC TRISC ; PIC17Cxxx SFR substitution
#define DDRD TRISD ; PIC17Cxxx SFR substitution
#define DDRE TRISE ; PIC17Cxxx SFR substitution
;==========================================================================
;
; Register Definitions
;
;==========================================================================
;----- Register Files -----------------------------------------------------
PORTA EQU H'0F80'
PORTB EQU H'0F81'
PORTC EQU H'0F82'
LATA EQU H'0F89'
LATB EQU H'0F8A'
LATC EQU H'0F8B'
DDRA EQU H'0F92'
TRISA EQU H'0F92'
DDRB EQU H'0F93'
TRISB EQU H'0F93'
DDRC EQU H'0F94'
TRISC EQU H'0F94'
OSCTUNE EQU H'0F9B'
PIE1 EQU H'0F9D'
PIR1 EQU H'0F9E'
IPR1 EQU H'0F9F'
PIE2 EQU H'0FA0'
PIR2 EQU H'0FA1'
IPR2 EQU H'0FA2'
EECON1 EQU H'0FA6'
EECON2 EQU H'0FA7'
RCSTA EQU H'0FAB'
RCSTA1 EQU H'0FAB'
TXSTA EQU H'0FAC'
TXSTA1 EQU H'0FAC'
TXREG EQU H'0FAD'
TXREG1 EQU H'0FAD'
RCREG EQU H'0FAE'
RCREG1 EQU H'0FAE'
SPBRG EQU H'0FAF'
SPBRG1 EQU H'0FAF'
SPBRGH EQU H'0FB0'
CMCON EQU H'0FB4'
CVRCON EQU H'0FB5'
ECCP1AS EQU H'0FB6'
ECCP1DEL EQU H'0FB7'
PWM1CON EQU H'0FB7'
BAUDCON EQU H'0FB8'
BAUDCTL EQU H'0FB8'
CCP2CON EQU H'0FBA'
CCPR2 EQU H'0FBB'
CCPR2L EQU H'0FBB'
CCPR2H EQU H'0FBC'
CCP1CON EQU H'0FBD'
CCPR1 EQU H'0FBE'
CCPR1L EQU H'0FBE'
CCPR1H EQU H'0FBF'
ADCON2 EQU H'0FC0'
ADCON1 EQU H'0FC1'
ADCON0 EQU H'0FC2'
ADRES EQU H'0FC3'
ADRESL EQU H'0FC3'
ADRESH EQU H'0FC4'
SSP1CON2 EQU H'0FC5'
SSPCON2 EQU H'0FC5'
SSP1CON1 EQU H'0FC6'
SSPCON1 EQU H'0FC6'
SSP1STAT EQU H'0FC7'
SSPSTAT EQU H'0FC7'
SSP1ADD EQU H'0FC8'
SSPADD EQU H'0FC8'
SSP1BUF EQU H'0FC9'
SSPBUF EQU H'0FC9'
T2CON EQU H'0FCA'
PR2 EQU H'0FCB'
TMR2 EQU H'0FCC'
T1CON EQU H'0FCD'
TMR1L EQU H'0FCE'
TMR1H EQU H'0FCF'
RCON EQU H'0FD0'
WDTCON EQU H'0FD1'
OSCCON EQU H'0FD3'
T0CON EQU H'0FD5'
TMR0L EQU H'0FD6'
TMR0H EQU H'0FD7'
STATUS EQU H'0FD8'
FSR2L EQU H'0FD9'
FSR2H EQU H'0FDA'
PLUSW2 EQU H'0FDB'
PREINC2 EQU H'0FDC'
POSTDEC2 EQU H'0FDD'
POSTINC2 EQU H'0FDE'
INDF2 EQU H'0FDF'
BSR EQU H'0FE0'
FSR1L EQU H'0FE1'
FSR1H EQU H'0FE2'
PLUSW1 EQU H'0FE3'
PREINC1 EQU H'0FE4'
POSTDEC1 EQU H'0FE5'
POSTINC1 EQU H'0FE6'
INDF1 EQU H'0FE7'
WREG EQU H'0FE8'
FSR0L EQU H'0FE9'
FSR0H EQU H'0FEA'
PLUSW0 EQU H'0FEB'
PREINC0 EQU H'0FEC'
POSTDEC0 EQU H'0FED'
POSTINC0 EQU H'0FEE'
INDF0 EQU H'0FEF'
INTCON3 EQU H'0FF0'
INTCON2 EQU H'0FF1'
INTCON EQU H'0FF2'
PROD EQU H'0FF3'
PRODL EQU H'0FF3'
PRODH EQU H'0FF4'
TABLAT EQU H'0FF5'
TBLPTR EQU H'0FF6'
TBLPTRL EQU H'0FF6'
TBLPTRH EQU H'0FF7'
TBLPTRU EQU H'0FF8'
PC EQU H'0FF9'
PCL EQU H'0FF9'
PCLATH EQU H'0FFA'
PCLATU EQU H'0FFB'
STKPTR EQU H'0FFC'
TOS EQU H'0FFD'
TOSL EQU H'0FFD'
TOSH EQU H'0FFE'
TOSU EQU H'0FFF'
;----- PORTA Bits -----------------------------------------------------
RA0 EQU H'0000'
RA1 EQU H'0001'
RA2 EQU H'0002'
RA3 EQU H'0003'
RA5 EQU H'0005'
AN0 EQU H'0000'
AN1 EQU H'0001'
AN2 EQU H'0002'
AN3 EQU H'0003'
AN4 EQU H'0005'
VREFM EQU H'0002'
VREFP EQU H'0003'
SS1 EQU H'0005'
CVREF EQU H'0002'
C2OUT_PORTA EQU H'0005'
NOT_SS1 EQU H'0005'
;----- PORTB Bits -----------------------------------------------------
RB0 EQU H'0000'
RB1 EQU H'0001'
RB2 EQU H'0002'
RB3 EQU H'0003'
RB4 EQU H'0004'
RB5 EQU H'0005'
RB6 EQU H'0006'
RB7 EQU H'0007'
INT0 EQU H'0000'
INT1 EQU H'0001'
INT2 EQU H'0002'
CCP2_PORTB EQU H'0003'
KBI0 EQU H'0004'
KBI1 EQU H'0005'
KBI2 EQU H'0006'
KBI3 EQU H'0007'
PGC EQU H'0006'
PGD EQU H'0007'
AN12 EQU H'0000'
AN10 EQU H'0001'
AN8 EQU H'0002'
AN9 EQU H'0003'
AN11 EQU H'0004'
T0CKI EQU H'0005'
FLT0 EQU H'0000'
C1OUT_PORTB EQU H'0005'
;----- PORTC Bits -----------------------------------------------------
RC0 EQU H'0000'
RC1 EQU H'0001'
RC2 EQU H'0002'
RC3 EQU H'0003'
RC4 EQU H'0004'
RC5 EQU H'0005'
RC6 EQU H'0006'
RC7 EQU H'0007'
T1OSO EQU H'0000'
T1OSI EQU H'0001'
CCP1 EQU H'0002'
SCK1 EQU H'0003'
SDI1 EQU H'0004'
SDO1 EQU H'0005'
TX EQU H'0006'
RX EQU H'0007'
T1CKI EQU H'0000'
CCP2_PORTC EQU H'0001'
P1A EQU H'0002'
SCL1 EQU H'0003'
SDA1 EQU H'0004'
CK EQU H'0006'
; DT is a reserved word
; DT EQU H'0007'
SCK EQU H'0003'
SDI EQU H'0004'
SDO EQU H'0005'
SCL EQU H'0003'
SDA EQU H'0004'
;----- LATA Bits -----------------------------------------------------
LATA0 EQU H'0000'
LATA1 EQU H'0001'
LATA2 EQU H'0002'
LATA3 EQU H'0003'
LATA5 EQU H'0005'
;----- LATB Bits -----------------------------------------------------
LATB0 EQU H'0000'
LATB1 EQU H'0001'
LATB2 EQU H'0002'
LATB3 EQU H'0003'
LATB4 EQU H'0004'
LATB5 EQU H'0005'
LATB6 EQU H'0006'
LATB7 EQU H'0007'
;----- LATC Bits -----------------------------------------------------
LATC0 EQU H'0000'
LATC1 EQU H'0001'
LATC2 EQU H'0002'
LATC3 EQU H'0003'
LATC4 EQU H'0004'
LATC5 EQU H'0005'
LATC6 EQU H'0006'
LATC7 EQU H'0007'
;----- DDRA Bits -----------------------------------------------------
RA0 EQU H'0000'
RA1 EQU H'0001'
RA2 EQU H'0002'
RA3 EQU H'0003'
RA5 EQU H'0005'
;----- TRISA Bits -----------------------------------------------------
TRISA0 EQU H'0000'
TRISA1 EQU H'0001'
TRISA2 EQU H'0002'
TRISA3 EQU H'0003'
TRISA5 EQU H'0005'
;----- DDRB Bits -----------------------------------------------------
RB0 EQU H'0000'
RB1 EQU H'0001'
RB2 EQU H'0002'
RB3 EQU H'0003'
RB4 EQU H'0004'
RB5 EQU H'0005'
RB6 EQU H'0006'
RB7 EQU H'0007'
;----- TRISB Bits -----------------------------------------------------
TRISB0 EQU H'0000'
TRISB1 EQU H'0001'
TRISB2 EQU H'0002'
TRISB3 EQU H'0003'
TRISB4 EQU H'0004'
TRISB5 EQU H'0005'
TRISB6 EQU H'0006'
TRISB7 EQU H'0007'
;----- DDRC Bits -----------------------------------------------------
RC0 EQU H'0000'
RC1 EQU H'0001'
RC2 EQU H'0002'
RC3 EQU H'0003'
RC4 EQU H'0004'
RC5 EQU H'0005'
RC6 EQU H'0006'
RC7 EQU H'0007'
;----- TRISC Bits -----------------------------------------------------
TRISC0 EQU H'0000'
TRISC1 EQU H'0001'
TRISC2 EQU H'0002'
TRISC3 EQU H'0003'
TRISC4 EQU H'0004'
TRISC5 EQU H'0005'
TRISC6 EQU H'0006'
TRISC7 EQU H'0007'
;----- OSCTUNE Bits -----------------------------------------------------
PLLEN EQU H'0006'
;----- PIE1 Bits -----------------------------------------------------
TMR1IE EQU H'0000'
TMR2IE EQU H'0001'
CCP1IE EQU H'0002'
SSPIE EQU H'0003'
TXIE EQU H'0004'
RCIE EQU H'0005'
ADIE EQU H'0006'
SSP1IE EQU H'0003'
TX1IE EQU H'0004'
RC1IE EQU H'0005'
;----- PIR1 Bits -----------------------------------------------------
TMR1IF EQU H'0000'
TMR2IF EQU H'0001'
CCP1IF EQU H'0002'
SSPIF EQU H'0003'
TXIF EQU H'0004'
RCIF EQU H'0005'
ADIF EQU H'0006'
SSP1IF EQU H'0003'
TX1IF EQU H'0004'
RC1IF EQU H'0005'
;----- IPR1 Bits -----------------------------------------------------
TMR1IP EQU H'0000'
TMR2IP EQU H'0001'
CCP1IP EQU H'0002'
SSPIP EQU H'0003'
TXIP EQU H'0004'
RCIP EQU H'0005'
ADIP EQU H'0006'
SSP1IP EQU H'0003'
TX1IP EQU H'0004'
RC1IP EQU H'0005'
;----- PIE2 Bits -----------------------------------------------------
CCP2IE EQU H'0000'
BCLIE EQU H'0003'
CMIE EQU H'0006'
OSCFIE EQU H'0007'
BCL1IE EQU H'0003'
;----- PIR2 Bits -----------------------------------------------------
CCP2IF EQU H'0000'
BCLIF EQU H'0003'
CMIF EQU H'0006'
OSCFIF EQU H'0007'
BCL1IF EQU H'0003'
;----- IPR2 Bits -----------------------------------------------------
CCP2IP EQU H'0000'
BCLIP EQU H'0003'
CMIP EQU H'0006'
OSCFIP EQU H'0007'
BCL1IP EQU H'0003'
;----- EECON1 Bits -----------------------------------------------------
WR EQU H'0001'
WREN EQU H'0002'
WRERR EQU H'0003'
FREE EQU H'0004'
;----- RCSTA Bits -----------------------------------------------------
RX9D EQU H'0000'
OERR EQU H'0001'
FERR EQU H'0002'
ADDEN EQU H'0003'
CREN EQU H'0004'
SREN EQU H'0005'
RX9 EQU H'0006'
SPEN EQU H'0007'
RCD8 EQU H'0000'
ADEN EQU H'0003'
RC9 EQU H'0006'
NOT_RC8 EQU H'0006'
RC8_9 EQU H'0006'
;----- RCSTA1 Bits -----------------------------------------------------
RX9D EQU H'0000'
OERR EQU H'0001'
FERR EQU H'0002'
ADDEN EQU H'0003'
CREN EQU H'0004'
SREN EQU H'0005'
RX9 EQU H'0006'
SPEN EQU H'0007'
RCD8 EQU H'0000'
RC9 EQU H'0006'
NOT_RC8 EQU H'0006'
RC8_9 EQU H'0006'
;----- TXSTA Bits -----------------------------------------------------
TX9D EQU H'0000'
TRMT EQU H'0001'
BRGH EQU H'0002'
SENDB EQU H'0003'
SYNC EQU H'0004'
TXEN EQU H'0005'
TX9 EQU H'0006'
CSRC EQU H'0007'
TXD8 EQU H'0000'
TX8_9 EQU H'0006'
NOT_TX8 EQU H'0006'
;----- TXSTA1 Bits -----------------------------------------------------
TX9D EQU H'0000'
TRMT EQU H'0001'
BRGH EQU H'0002'
SENDB EQU H'0003'
SYNC EQU H'0004'
TXEN EQU H'0005'
TX9 EQU H'0006'
CSRC EQU H'0007'
TXD8 EQU H'0000'
TX8_9 EQU H'0006'
NOT_TX8 EQU H'0006'
;----- CMCON Bits -----------------------------------------------------
CM0 EQU H'0000'
CM1 EQU H'0001'
CM2 EQU H'0002'
CIS EQU H'0003'
C1INV EQU H'0004'
C2INV EQU H'0005'
C1OUT_CMCON EQU H'0006'
C2OUT_CMCON EQU H'0007'
;----- CVRCON Bits -----------------------------------------------------
CVR0 EQU H'0000'
CVR1 EQU H'0001'
CVR2 EQU H'0002'
CVR3 EQU H'0003'
CVRSS EQU H'0004'
CVRR EQU H'0005'
CVROE EQU H'0006'
CVREN EQU H'0007'
;----- ECCP1AS Bits -----------------------------------------------------
PSSAC0 EQU H'0002'
PSSAC1 EQU H'0003'
ECCPAS0 EQU H'0004'
ECCPAS1 EQU H'0005'
ECCPAS2 EQU H'0006'
ECCPASE EQU H'0007'
;----- ECCP1DEL Bits -----------------------------------------------------
PRSEN EQU H'0007'
;----- PWM1CON Bits -----------------------------------------------------
PRSEN EQU H'0007'
;----- BAUDCON Bits -----------------------------------------------------
ABDEN EQU H'0000'
WUE EQU H'0001'
BRG16 EQU H'0003'
SCKP EQU H'0004'
RCIDL EQU H'0006'
ABDOVF EQU H'0007'
RCMT EQU H'0006'
;----- BAUDCTL Bits -----------------------------------------------------
ABDEN EQU H'0000'
WUE EQU H'0001'
BRG16 EQU H'0003'
SCKP EQU H'0004'
RCIDL EQU H'0006'
ABDOVF EQU H'0007'
RCMT EQU H'0006'
;----- CCP2CON Bits -----------------------------------------------------
CCP2M0 EQU H'0000'
CCP2M1 EQU H'0001'
CCP2M2 EQU H'0002'
CCP2M3 EQU H'0003'
DC2B0 EQU H'0004'
DC2B1 EQU H'0005'
CCP2Y EQU H'0004'
CCP2X EQU H'0005'
;----- CCP1CON Bits -----------------------------------------------------
CCP1M0 EQU H'0000'
CCP1M1 EQU H'0001'
CCP1M2 EQU H'0002'
CCP1M3 EQU H'0003'
DC1B0 EQU H'0004'
DC1B1 EQU H'0005'
CCP1Y EQU H'0004'
CCP1X EQU H'0005'
;----- ADCON2 Bits -----------------------------------------------------
ADCS0 EQU H'0000'
ADCS1 EQU H'0001'
ADCS2 EQU H'0002'
ACQT0 EQU H'0003'
ACQT1 EQU H'0004'
ACQT2 EQU H'0005'
ADFM EQU H'0007'
;----- ADCON1 Bits -----------------------------------------------------
PCFG0 EQU H'0000'
PCFG1 EQU H'0001'
PCFG2 EQU H'0002'
PCFG3 EQU H'0003'
VCFG0 EQU H'0004'
VCFG1 EQU H'0005'
;----- ADCON0 Bits -----------------------------------------------------
DONE EQU H'0001'
GO_DONE EQU H'0001'
ADON EQU H'0000'
GO EQU H'0001'
CHS0 EQU H'0002'
CHS1 EQU H'0003'
CHS2 EQU H'0004'
CHS3 EQU H'0005'
ADCAL EQU H'0007'
NOT_DONE EQU H'0001'
;----- SSP1CON2 Bits -----------------------------------------------------
SEN EQU H'0000'
RSEN EQU H'0001'
PEN EQU H'0002'
RCEN EQU H'0003'
ACKEN EQU H'0004'
ACKDT EQU H'0005'
ACKSTAT EQU H'0006'
GCEN EQU H'0007'
;----- SSPCON2 Bits -----------------------------------------------------
SEN EQU H'0000'
RSEN EQU H'0001'
PEN EQU H'0002'
RCEN EQU H'0003'
ACKEN EQU H'0004'
ACKDT EQU H'0005'
ACKSTAT EQU H'0006'
GCEN EQU H'0007'
;----- SSP1CON1 Bits -----------------------------------------------------
SSPM0 EQU H'0000'
SSPM1 EQU H'0001'
SSPM2 EQU H'0002'
SSPM3 EQU H'0003'
CKP EQU H'0004'
SSPEN EQU H'0005'
SSPOV EQU H'0006'
WCOL EQU H'0007'
;----- SSPCON1 Bits -----------------------------------------------------
SSPM0 EQU H'0000'
SSPM1 EQU H'0001'
SSPM2 EQU H'0002'
SSPM3 EQU H'0003'
CKP EQU H'0004'
SSPEN EQU H'0005'
SSPOV EQU H'0006'
WCOL EQU H'0007'
;----- SSP1STAT Bits -----------------------------------------------------
BF EQU H'0000'
UA EQU H'0001'
R_W EQU H'0002'
S EQU H'0003'
P EQU H'0004'
D_A EQU H'0005'
CKE EQU H'0006'
SMP EQU H'0007'
I2C_READ EQU H'0002'
I2C_START EQU H'0003'
I2C_STOP EQU H'0004'
I2C_DAT EQU H'0005'
NOT_W EQU H'0002'
NOT_A EQU H'0005'
NOT_WRITE EQU H'0002'
NOT_ADDRESS EQU H'0005'
READ_WRITE EQU H'0002'
DATA_ADDRESS EQU H'0005'
R EQU H'0002'
D EQU H'0005'
;----- SSPSTAT Bits -----------------------------------------------------
BF EQU H'0000'
UA EQU H'0001'
R_W EQU H'0002'
S EQU H'0003'
P EQU H'0004'
D_A EQU H'0005'
CKE EQU H'0006'
SMP EQU H'0007'
I2C_READ EQU H'0002'
I2C_START EQU H'0003'
I2C_STOP EQU H'0004'
I2C_DAT EQU H'0005'
NOT_W EQU H'0002'
NOT_A EQU H'0005'
NOT_WRITE EQU H'0002'
NOT_ADDRESS EQU H'0005'
READ_WRITE EQU H'0002'
DATA_ADDRESS EQU H'0005'
R EQU H'0002'
D EQU H'0005'
;----- T2CON Bits -----------------------------------------------------
T2CKPS0 EQU H'0000'
T2CKPS1 EQU H'0001'
TMR2ON EQU H'0002'
T2OUTPS0 EQU H'0003'
T2OUTPS1 EQU H'0004'
T2OUTPS2 EQU H'0005'
T2OUTPS3 EQU H'0006'
TOUTPS0 EQU H'0003'
TOUTPS1 EQU H'0004'
TOUTPS2 EQU H'0005'
TOUTPS3 EQU H'0006'
;----- T1CON Bits -----------------------------------------------------
TMR1ON EQU H'0000'
TMR1CS EQU H'0001'
T1SYNC EQU H'0002'
T1OSCEN EQU H'0003'
T1CKPS0 EQU H'0004'
T1CKPS1 EQU H'0005'
T1RUN EQU H'0006'
RD16 EQU H'0007'
T1INSYNC EQU H'0002'
NOT_T1SYNC EQU H'0002'
;----- RCON Bits -----------------------------------------------------
NOT_BOR EQU H'0000'
NOT_POR EQU H'0001'
NOT_PD EQU H'0002'
NOT_TO EQU H'0003'
NOT_RI EQU H'0004'
IPEN EQU H'0007'
BOR EQU H'0000'
POR EQU H'0001'
PD EQU H'0002'
TO EQU H'0003'
RI EQU H'0004'
;----- WDTCON Bits -----------------------------------------------------
SWDTE EQU H'0000'
SWDTEN EQU H'0000'
;----- OSCCON Bits -----------------------------------------------------
SCS0 EQU H'0000'
SCS1 EQU H'0001'
OSTS EQU H'0003'
IDLEN EQU H'0007'
;----- T0CON Bits -----------------------------------------------------
T0PS0 EQU H'0000'
T0PS1 EQU H'0001'
T0PS2 EQU H'0002'
PSA EQU H'0003'
T0SE EQU H'0004'
T0CS EQU H'0005'
T08BIT EQU H'0006'
TMR0ON EQU H'0007'
;----- STATUS Bits -----------------------------------------------------
C EQU H'0000'
DC EQU H'0001'
Z EQU H'0002'
OV EQU H'0003'
N EQU H'0004'
;----- INTCON3 Bits -----------------------------------------------------
INT1F EQU H'0000'
INT2F EQU H'0001'
INT1E EQU H'0003'
INT2E EQU H'0004'
INT1P EQU H'0006'
INT2P EQU H'0007'
INT1IF EQU H'0000'
INT2IF EQU H'0001'
INT1IE EQU H'0003'
INT2IE EQU H'0004'
INT1IP EQU H'0006'
INT2IP EQU H'0007'
;----- INTCON2 Bits -----------------------------------------------------
RBIP EQU H'0000'
T0IP EQU H'0002'
INTEDG2 EQU H'0004'
INTEDG1 EQU H'0005'
INTEDG0 EQU H'0006'
NOT_RBPU EQU H'0007'
TMR0IP EQU H'0002'
RBPU EQU H'0007'
;----- INTCON Bits -----------------------------------------------------
RBIF EQU H'0000'
INT0F EQU H'0001'
T0IF EQU H'0002'
RBIE EQU H'0003'
INT0E EQU H'0004'
T0IE EQU H'0005'
PEIE EQU H'0006'
GIE EQU H'0007'
INT0IF EQU H'0001'
TMR0IF EQU H'0002'
INT0IE EQU H'0004'
TMR0IE EQU H'0005'
GIEL EQU H'0006'
GIEH EQU H'0007'
;----- STKPTR Bits -----------------------------------------------------
STKPTR0 EQU H'0000'
STKPTR1 EQU H'0001'
STKPTR2 EQU H'0002'
STKPTR3 EQU H'0003'
STKPTR4 EQU H'0004'
STKUNF EQU H'0006'
STKOVF EQU H'0007'
STKFUL EQU H'0007'
;==========================================================================
;
; RAM Definitions
;
;==========================================================================
__MAXRAM H'0FFF'
__BADRAM H'0400'-H'0F7F'
__BADRAM H'0F83'-H'0F88'
__BADRAM H'0F8C'-H'0F91'
__BADRAM H'0F95'-H'0F9A'
__BADRAM H'0F9C'
__BADRAM H'0FA3'-H'0FA5'
__BADRAM H'0FA8'-H'0FAA'
__BADRAM H'0FB1'-H'0FB3'
__BADRAM H'0FB9'
__BADRAM H'0FD2'
__BADRAM H'0FD4'
;==========================================================================
;
; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been
; superseded by the CONFIG directive. The following settings
; are available for this device.
;
; Background Debugger Enable bit:
; DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug
; DEBUG = OFF Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins
;
; Extended Instruction Set Enable bit:
; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
; XINST = ON Instruction set extension and Indexed Addressing mode enabled
;
; Stack Overflow/Underflow Reset Enable bit:
; STVREN = OFF Reset on stack overflow/underflow disabled
; STVREN = ON Reset on stack overflow/underflow enabled
;
; Watchdog Timer Enable bit:
; WDTEN = OFF WDT disabled (control is placed on SWDTEN bit)
; WDTEN = ON WDT enabled
;
; Code Protection bit:
; CP0 = ON Program memory is code-protected
; CP0 = OFF Program memory is not code-protected
;
; Fail-Safe Clock Monitor Enable bit:
; FCMEN = OFF Fail-Safe Clock Monitor disabled
; FCMEN = ON Fail-Safe Clock Monitor enabled
;
; Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit:
; IESO = OFF Two-Speed Start-up disabled
; IESO = ON Two-Speed Start-up enabled
;
; Default/Reset System Clock Select bit:
; FOSC2 = OFF INTRC enabled as system clock when OSCCON<1:0> = 00
; FOSC2 = ON Clock selected by FOSC as system clock is enabled when OSCCON<1:0> = 00
;
; Oscillator Selection bits:
; FOSC = HS HS oscillator
; FOSC = HSPLL HS oscillator, PLL enabled and under software control
; FOSC = EC EC oscillator, CLKO function on OSC2
; FOSC = ECPLL EC oscillator, PLL enabled and under software control, CLKO function on OSC2
;
; Watchdog Timer Postscale Select bits:
; WDTPS = 1 1:1
; WDTPS = 2 1:2
; WDTPS = 4 1:4
; WDTPS = 8 1:8
; WDTPS = 16 1:16
; WDTPS = 32 1:32
; WDTPS = 64 1:64
; WDTPS = 128 1:128
; WDTPS = 256 1:256
; WDTPS = 512 1:512
; WDTPS = 1024 1:1024
; WDTPS = 2048 1:2048
; WDTPS = 4096 1:4096
; WDTPS = 8192 1:8192
; WDTPS = 16384 1:16384
; WDTPS = 32768 1:32768
;
; CCP2 MUX bit:
; CCP2MX = ALTERNATE CCP2 is multiplexed with RB3
; CCP2MX = DEFAULT CCP2 is multiplexed with RC1
;
;==========================================================================
_DEVID1 EQU H'3FFFFE'
_DEVID2 EQU H'3FFFFF'
LIST
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