/usr/aarch64-linux-gnu/include/fpu_control.h is in libc6-dev-arm64-cross 2.19-0ubuntu2cross0.10.
This file is owned by root:root, with mode 0o644.
The actual contents of the file can be viewed below.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 | /* Copyright (C) 1996-2014 Free Software Foundation, Inc.
This file is part of the GNU C Library.
The GNU C Library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public License as
published by the Free Software Foundation; either version 2.1 of the
License, or (at your option) any later version.
The GNU C Library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with the GNU C Library; if not, see
<http://www.gnu.org/licenses/>. */
#ifndef _AARCH64_FPU_CONTROL_H
#define _AARCH64_FPU_CONTROL_H
/* Macros for accessing the FPCR and FPSR. */
#define _FPU_GETCW(fpcr) \
__asm__ __volatile__ ("mrs %0, fpcr" : "=r" (fpcr))
#define _FPU_SETCW(fpcr) \
{ \
__asm__ __volatile__ ("msr fpcr, %0" : : "r" (fpcr)); \
__asm__ __volatile__ ("isb"); \
}
#define _FPU_GETFPSR(fpsr) \
__asm__ __volatile__ ("mrs %0, fpsr" : "=r" (fpsr))
#define _FPU_SETFPSR(fpsr) \
__asm__ __volatile__ ("msr fpsr, %0" : : "r" (fpsr))
/* Reserved bits should be preserved when modifying register
contents. These two masks indicate which bits in each of FPCR and
FPSR should not be changed. */
#define _FPU_RESERVED 0xfe0fe0ff
#define _FPU_FPSR_RESERVED 0x0fffffe0
#define _FPU_DEFAULT 0x00000000
#define _FPU_FPSR_DEFAULT 0x00000000
/* Layout of FPCR and FPSR:
| | | | | | | |
0 0 0 0 1 1 1 0 0 0 0 0 1 0 0 0 1 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0
s s s s s s s s s s s
c c c c c c c c c c c c
N Z C V Q A D F R R S S S L L L I U U I U O D I I U U I U O D I
C H N Z M M T T B E E E D N N X F F Z O D N N X F F Z O
P O O R R Z N N N E K K E E E E E C K K C C C C C
D D I I P
E E D D
E E
*/
#define _FPU_FPCR_RM_MASK 0xc00000
#define _FPU_FPCR_MASK_IXE 0x1000
#define _FPU_FPCR_MASK_UFE 0x0800
#define _FPU_FPCR_MASK_OFE 0x0400
#define _FPU_FPCR_MASK_DZE 0x0200
#define _FPU_FPCR_MASK_IOE 0x0100
#define _FPU_FPCR_IEEE \
(_FPU_DEFAULT | _FPU_FPCR_MASK_IXE | \
_FPU_FPCR_MASK_UFE | _FPU_FPCR_MASK_OFE | \
_FPU_FPCR_MASK_DZE | _FPU_FPCR_MASK_IOE)
#define _FPU_FPSR_IEEE 0
typedef unsigned int fpu_control_t;
typedef unsigned int fpu_fpsr_t;
/* Default control word set at startup. */
extern fpu_control_t __fpu_control;
#endif
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