/usr/include/gpsim/14bit-instructions.h is in gpsim-dev 0.26.1-1.
This file is owned by root:root, with mode 0o644.
The actual contents of the file can be viewed below.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 | /*
Copyright (C) 1998 T. Scott Dattalo
This file is part of the libgpsim library of gpsim
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, see
<http://www.gnu.org/licenses/lgpl-2.1.html>.
*/
class instruction; // forward declaration for the include files that follow
#ifndef __14BIT_INSTRUCTIONS_H__
#define __14BIT_INSTRUCTIONS_H__
#define REG_IN_INSTRUCTION_MASK 0x7f
#define DESTINATION_MASK 0x80
#include "pic-instructions.h"
#include "12bit-instructions.h"
#include "14bit-registers.h"
//---------------------------------------------------------
class ADDLW : public Literal_op
{
public:
ADDLW(Processor *new_cpu, unsigned int new_opcode, unsigned int address);
virtual void execute(void);
static instruction *construct(Processor *new_cpu, unsigned int new_opcode, unsigned int address)
{return new ADDLW(new_cpu,new_opcode, address);}
};
//---------------------------------------------------------
class RETFIE : public instruction
{
public:
RETFIE(Processor *new_cpu, unsigned int new_opcode, unsigned int address);
virtual void execute(void);
virtual bool isBase() { return true;}
static instruction *construct(Processor *new_cpu, unsigned int new_opcode, unsigned int address)
{return new RETFIE(new_cpu,new_opcode,address);}
};
//---------------------------------------------------------
class RETURN : public instruction
{
public:
RETURN(Processor *new_cpu, unsigned int new_opcode, unsigned int address);
virtual void execute(void);
virtual bool isBase() { return true;}
static instruction *construct(Processor *new_cpu, unsigned int new_opcode, unsigned int address)
{return new RETURN(new_cpu,new_opcode,address);}
};
//---------------------------------------------------------
class SUBLW : public Literal_op
{
public:
SUBLW(Processor *new_cpu, unsigned int new_opcode, unsigned int address);
virtual void execute(void);
static instruction *construct(Processor *new_cpu, unsigned int new_opcode, unsigned int address)
{return new SUBLW(new_cpu,new_opcode,address);}
};
#endif // __14BIT_INSTRUCTIONS_H__
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