/usr/share/highlight/langDefs/vhd.lang is in highlight-common 3.41-1.
This file is owned by root:root, with mode 0o644.
The actual contents of the file can be viewed below.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 | Description="VHDL"
Keywords={
{ Id=1,
List={"abs", "access", "after", "all", "and", "architecture", "array",
"assert", "attribute", "begin", "block", "body", "buffer", "bus", "case",
"component", "configuration", "disconnect", "downto", "else", "elsif", "end",
"entity", "exit", "file", "for", "function", "generate", "generic", "group",
"guarded", "if", "impure", "in", "inertial", "inout", "is", "label", "library",
"linkage", "literal", "loop", "map", "mod", "nand", "new", "next", "nor", "not",
"null", "of", "on", "open", "or", "others", "out", "package", "port",
"postponed", "procedure", "process", "pure", "range", "record", "register",
"reject", "rem", "report", "return", "rol", "ror", "select", "severity",
"shared", "sla", "sll", "sra", "srl", "then", "to", "transport", "unaffected",
"units", "until", "use", "wait", "when", "while", "with", "xnor", "xor",
"activpullup", "andn", "and2ff", "andnff", "cnt1bit", "cntnbit", "cntnbitdown",
"cntnbitmod", "cntnbitoe", "cntnbitsld", "cntnbitsr", "cntnbitupdown",
"compnbit", "compnbitff", "diffh2lwithff", "diffl2hwithff", "dff1",
"dff1negclk", "dffn", "encode4to5", "mux1of2", "mux1of8", "mux1vof2v",
"mux1vof3v", "mux1vof4v", "prescale1bit", "prescale1bitar",
"prescale1bitarnegclk", "prescalenbit", "prescalenbitar", "reg1bit",
"reg1bitar", "reg1bitr", "regnbit", "regnbitar", "rsffasync", "rsffsync",
"rssynchronizer", "shiftp2sregnbitar", "shiftregnbitar", "shifts2sregnbit",
"srffsync", "syncanddiffl2hwithff", "syncanddiffh2lwithff",
"syncanddiffl2hwithffandfg", "syncanddiffh2lwithffandfg",
"syncanddiffll2hhwithff", "syncanddiffhh2llwithff",
"syncanddiffll2hhwithffandfg", "syncanddiffhh2llwithffandfg",
"activpullup_arch", "andn_arch", "and2ff_arch", "andnff_arch", "cnt1bit_arch",
"cntnbit_arch", "cntnbitdown_arch", "cntnbitmod_arch", "cntnbitoe_arch",
"cntnbitsld_arch", "cntnbitsr_arch", "cntnbitupdown_arch", "compnbit_arch",
"compnbitff_arch", "diffh2lwithff_arch", "diffl2hwithff_arch", "dff1_arch",
"dff1negclk_arch", "dffn_arch", "encode4to5_arch", "mux1of2_arch",
"mux1of8_arch", "mux1vof2v_arch", "mux1vof3v_arch", "mux1vof4v_arch",
"prescale1bit_arch", "prescale1bitar_arch", "prescale1bitarnegclk_arch",
"prescalenbit_arch", "prescalenbitar_arch", "reg1bit_arch", "reg1bitar_arch",
"reg1bitr_arch", "regnbit_arch", "regnbitar_arch", "rsffasync_arch",
"rsffsync_arch", "rssynchronizer_arch", "shiftp2sregnbitar_arch",
"shiftregnbitar_arch", "shifts2sregnbit_arch", "srffsync_arch",
"syncanddiffl2hwithff_arch", "syncanddiffh2lwithff_arch",
"syncanddiffl2hwithffandfg_arch", "syncanddiffh2lwithffandfg_arch",
"syncanddiffll2hhwithff_arch", "syncanddiffhh2llwithff_arch",
"syncanddiffll2hhwithffandfg_arch", "syncanddiffhh2llwithffandfg_arch"},
},
{ Id=2,
List={ "bit", "bit_vector", "boolean", "integer", "real", "std_logic",
"std_logic_vector", "time", "character", "string"},
},
{ Id=3,
List={"alias", "constant", "type", "variable", "signal", "subtype"},
},
{ Id=4,
Regex=[[[\w\(\)]+('\w+)]],
},
}
Strings={
Delimiter=[[']],
}
IgnoreCase=true
Comments={
{ Block=false,
Delimiter= { [[\-\-]] },
},
}
Operators=[[\(|\)|\[|\]|\{|\}|\,|\;|\:|\&|<|>|\!|\=|\/|\*|\%|\+|\-]]
|