/usr/include/atomic_ops/sysdeps/gcc/mips.h is in libatomic-ops-dev 7.4.2-1.
This file is owned by root:root, with mode 0o644.
The actual contents of the file can be viewed below.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 | /*
* Copyright (c) 2005,2007 Thiemo Seufer <ths@networkno.de>
*
* THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY EXPRESSED
* OR IMPLIED. ANY USE IS AT YOUR OWN RISK.
*
* Permission is hereby granted to use or copy this program
* for any purpose, provided the above notices are retained on all copies.
* Permission to modify the code and to distribute modified code is granted,
* provided the above notices are retained, and a notice that the code was
* modified is included with the above copyright notice.
*/
/*
* FIXME: This should probably make finer distinctions. SGI MIPS is
* much more strongly ordered, and in fact closer to sequentially
* consistent. This is really aimed at modern embedded implementations.
* It looks to me like this assumes a 32-bit ABI. -HB
*/
#include "../all_aligned_atomic_load_store.h"
#include "../loadstore/acquire_release_volatile.h"
#include "../test_and_set_t_is_ao_t.h"
/* Data dependence does not imply read ordering. */
#define AO_NO_DD_ORDERING
#ifdef AO_ICE9A1_LLSC_WAR
/* ICE9 rev A1 chip (used in very few systems) is reported to */
/* have a low-frequency bug that causes LL to fail. */
/* To workaround, just issue the second 'LL'. */
# define AO_MIPS_LL_FIX(args_str) \
" ll " args_str "\n"
#else
# define AO_MIPS_LL_FIX(args_str) ""
#endif
AO_INLINE void
AO_nop_full(void)
{
__asm__ __volatile__(
" .set push \n"
" .set mips2 \n"
" .set noreorder \n"
" .set nomacro \n"
" sync \n"
" .set pop "
: : : "memory");
}
#define AO_HAVE_nop_full
#ifndef AO_PREFER_GENERALIZED
AO_INLINE AO_t
AO_fetch_and_add(volatile AO_t *addr, AO_t incr)
{
register int result;
register int temp;
__asm__ __volatile__(
" .set push\n"
" .set mips2\n"
" .set noreorder\n"
" .set nomacro\n"
"1: ll %0, %2\n"
AO_MIPS_LL_FIX("%0, %2")
" addu %1, %0, %3\n"
" sc %1, %2\n"
" beqz %1, 1b\n"
" nop\n"
" .set pop "
: "=&r" (result), "=&r" (temp), "+m" (*addr)
: "Ir" (incr)
: "memory");
return (AO_t)result;
}
#define AO_HAVE_fetch_and_add
AO_INLINE AO_TS_VAL_t
AO_test_and_set(volatile AO_TS_t *addr)
{
register int oldval;
register int temp;
__asm__ __volatile__(
" .set push\n"
" .set mips2\n"
" .set noreorder\n"
" .set nomacro\n"
"1: ll %0, %2\n"
AO_MIPS_LL_FIX("%0, %2")
" move %1, %3\n"
" sc %1, %2\n"
" beqz %1, 1b\n"
" nop\n"
" .set pop "
: "=&r" (oldval), "=&r" (temp), "+m" (*addr)
: "r" (1)
: "memory");
return (AO_TS_VAL_t)oldval;
}
#define AO_HAVE_test_and_set
/* TODO: Implement AO_and/or/xor primitives directly. */
#endif /* !AO_PREFER_GENERALIZED */
#ifndef AO_GENERALIZE_ASM_BOOL_CAS
AO_INLINE int
AO_compare_and_swap(volatile AO_t *addr, AO_t old, AO_t new_val)
{
register int was_equal = 0;
register int temp;
__asm__ __volatile__(
" .set push \n"
" .set mips2 \n"
" .set noreorder \n"
" .set nomacro \n"
"1: ll %0, %1 \n"
AO_MIPS_LL_FIX("%0, %1")
" bne %0, %4, 2f \n"
" move %0, %3 \n"
" sc %0, %1 \n"
" .set pop \n"
" beqz %0, 1b \n"
" li %2, 1 \n"
"2: "
: "=&r" (temp), "+m" (*addr), "+r" (was_equal)
: "r" (new_val), "r" (old)
: "memory");
return was_equal;
}
# define AO_HAVE_compare_and_swap
#endif /* !AO_GENERALIZE_ASM_BOOL_CAS */
AO_INLINE AO_t
AO_fetch_compare_and_swap(volatile AO_t *addr, AO_t old, AO_t new_val)
{
register int fetched_val;
register int temp;
__asm__ __volatile__(
" .set push\n"
" .set mips2\n"
" .set noreorder\n"
" .set nomacro\n"
"1: ll %0, %2\n"
AO_MIPS_LL_FIX("%0, %2")
" bne %0, %4, 2f\n"
" move %1, %3\n"
" sc %1, %2\n"
" beqz %1, 1b\n"
" nop\n"
" .set pop\n"
"2:"
: "=&r" (fetched_val), "=&r" (temp), "+m" (*addr)
: "r" (new_val), "Jr" (old)
: "memory");
return (AO_t)fetched_val;
}
#define AO_HAVE_fetch_compare_and_swap
/* #include "../standard_ao_double_t.h" */
/* TODO: Implement double-wide operations if available. */
/* CAS primitives with acquire, release and full semantics are */
/* generated automatically (and AO_int_... primitives are */
/* defined properly after the first generalization pass). */
/* FIXME: 32-bit ABI is assumed. */
#define AO_T_IS_INT
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